1. Field of the Invention
The present invention generally relates to a time axis correcting device for use in a video tape player or the like, for minimizing or substantially eliminating change in time axis that is caused in a video signal as a result of a change in speed.
2. Description of the Background Art
FIG. 3 of the accompanying drawings illustrates a prior art time axis correcting device in a block circuit representation. This prior art time axis correcting device is disclosed in "VTR Gijutsu (VTR Technology)", page 118, edited by Nippon Hoso Shuppan Kyokai and comprises an analog-to-digital (A/D) converter 1, a memory unit 2, a digital-to-analog (D/A) converter 3, a write-in clock generator 4 and a read-out clock generator 5.
This prior art time axis correcting device operates in the following manner. Assuming that a video signal having its time axis varying is inputted to the write-in clock generator 4, the write-in clock generator 4 outputs a write-in clock signal conforming to the change in time axis. The write-in signal emerging from the write-in clock generator 4 is in turn applied to the analog-to-digital converter 1 which functions to sample the input video signal and converts the input video signal into a PCM signal, the sampled value being subsequently stored in the memory unit 2. On the other hand, in the read-out clock generator 5, a clock signal necessary to read out data from the memory unit 2 in synchronism with a reference synchronizing signal applied thereto from an external terminal 12 is synthesized. Therefore, in synchronism with the read-out clock signal generated from the read-out clock generator 5, the data stored in the memory unit 2 can be read out therefrom and is in turn supplied to the digital-to-analog converter 3 for the conversion of the data into an analog signal.
By the process described above, the change in time axis can be substantially removed from the input video signal and an output video signal having its time axis stabilized in synchronism with the external reference signal can be obtained.
The write-in clock generator referred to above is available in numerous models. For example, Japanese Laid-open Patent Publication No. 58-124385, published in 1983, discloses a write-in clock generator of a type wherein means is provided for detecting, and responding at a high speed to, change in time axis in dependence on a burst signal contained in the input video signal.
FIG. 4 illustrates a waveform used to explain the principle of detection of a deviation of sampling points resulting from the change in time axis. Referring to FIG. 4, if the cycle of a sine wave represented by the burst signal is four times the sampling cycle, the sampling of the burst signal will give four sampling points per cycle as shown. Assuming that the sampling points shown in FIG. 4 have respective levels expressed by X1, X2, X3 and X4, the following relationships can be established: EQU X1=B+A.multidot.sin .theta. EQU X2=B+A.multidot.sin (.theta.+90.degree.)=B+A.multidot.cos .theta. EQU X3=B+A.multidot.sin (.theta.+180.degree.)=B-A.multidot.sin .theta. EQU X4=B+A.multidot.sin (.theta.+270.degree.)=B-A.multidot.cos .theta.
wherein A represents the amplitude of the burst signal, B represents the direct current level of the burst signal and .theta. represents the phase of the sampling point corresponding to the level X1 of the sampling point. Accordingly, EQU X1-X3=2A.multidot.sin .theta.,
and EQU X2-X4=2A.multidot.cos .theta.
and, therefore, the phase .theta. of the sampling point can be determined from the four sampling points as expressed by the following equation: EQU .theta.=tan .sup.-1 (X1-X3)/(X2-X4).
If .theta.=0 is taken as the reference to the sampling point, the calculation of the phase .theta. of the sampling point can provide an indication of the deviation (phase difference) of the sampling point from the reference point. In view of this, by varying the phase of the sampling clock signal (sampling command signal) according to the calculated phase .theta. (phase difference) of the sampling point, the write-in clock can be obtained which corresponds to change in time axis.
The above mentioned patent publication also discloses a phase modulating means as a means for varying the phase of the sampling clock signal. This phase modulating means is reproduced in FIG. 5 in a block circuit representation. Referring now to FIG. 5, the phase modulating means includes delay elements 34, 35, 36, 37, 38 and 39, each of the delay elements 34 to 36 having a delay amount equal to 1/4 of the cycle of the sampling clock signal while each of the delay elements 37 to 39 has a delay amount equal to 1/16 of the cycle of the sampling clock signal. The phase modulating means disclosed therein also includes data selectors 31 and 32 and a buffer amplifier 33.
In the above described phase modulating means, the delay elements 34 to 36 weighted to have a delay amount equal to 1/4 of the cycle of the sampling clock signal are connected in series with each other with input and output terminals of each delay elements 34 to 36 connected to input terminals of the data selector 31, and similarly, the delay elements 37 to 39 weighted to have a delay amount equal to 1/16 of the cycle of the sampling clock signal are connected in series with each other with input and output terminals of each of the delay elements 37 to 39 connected to input terminals of the data selector 32. A reference clock signal is applied to an input of the phase modulating means through the buffer amplifier 33. This phase modulating means is so designed that a data corresponding to the amount of delay of the clock signal determined in reference to the phase .theta. of the sampling point so calculated by the above described method is applied, as a fine time axis error signal, to the data selectors 31 and 32 thereby to modulate the phase of the sampling clock signal.
In the prior art time axis correcting device of the construction described hereinabove, the circuit shown in and described with reference to FIG. 5 has been employed as a sampling clock modulating means capable of responding at high speed to the change in time axis contained in the input video signal. The use of the sampling clock modulating means of the type discussed above has a problem in that the amounts of delay exhibited by the data selectors 31 and 32 must be exactly matched with the delay characteristics of the delay elements 34 to 39, requiring time-consuming and cumbersome adjustment.